欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS1374-BWLT1214 参数 Datasheet PDF下载

AS1374-BWLT1214图片预览
型号: AS1374-BWLT1214
PDF下载: 下载PDF文件 查看货源
内容描述: 双路200mA ,低噪声,高PSRR ,低压降稳压器 [Dual 200mA, Low-Noise, High-PSRR, Low Dropout Regulators]
分类和应用: 稳压器
文件页数/大小: 19 页 / 1101 K
品牌: AMSCO [ AMS(艾迈斯) ]
 浏览型号AS1374-BWLT1214的Datasheet PDF文件第11页浏览型号AS1374-BWLT1214的Datasheet PDF文件第12页浏览型号AS1374-BWLT1214的Datasheet PDF文件第13页浏览型号AS1374-BWLT1214的Datasheet PDF文件第14页浏览型号AS1374-BWLT1214的Datasheet PDF文件第16页浏览型号AS1374-BWLT1214的Datasheet PDF文件第17页浏览型号AS1374-BWLT1214的Datasheet PDF文件第18页浏览型号AS1374-BWLT1214的Datasheet PDF文件第19页  
AS1374  
Datasheet  
9.6.5 Transient Response  
The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error  
loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output  
capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally:  
VTRANSIENT = IOUTPUT RESR Units are Volts, Amps, Ohms.  
(EQ 15)  
Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Do remember to keep the ESR within  
stability recommendations when reducing ESR by adding multiple parallel output capacitors.  
After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change.  
This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of:  
T
----------------  
VTRANSIENT = IOUTPUT RESR  
+
Units are Volts, Seconds, Farads, Ohms.  
(EQ
CLOAD  
Where:  
CLOAD is output capacitor  
T= Propagation Delay of the LDO  
This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of couse thformula holds for  
t < “propagation time”, so that a faster LDO needs a smaller cap at the load to chieve a similar transient responseFor intance 50mA load  
current step produces 50mV output drop if the LDO response is 1µsec and thload cap 1µF.  
There is also a steady state error caused by the finite output impedance of the reglator. This is derived from the lad regulation specification  
discussed above.  
9.6.6 Turn On Time  
This specification defines the time taken for the LDO to awake from shutdown. The time is mesured from the release of the enable pin to the  
time that the output voltage is within 5% of the final value. It assumethat the voltage at s stable and within the regulator min and max limits.  
Shutdown reduces the quiescent current to very low, mostlleakage values (<1A).  
9.6.7 Thermal Protection  
To prevent operation under extreme fault codins, such as a permanent sort circuit at the output, thermal protection is built into the device.  
Die temperature is measured, and when a 16hreshold is reachee devce enters shutdown. When the die cools sufficiently, the device  
will restart (assuming input voltage exists and the device is enabled)esis of 15°C prevents low frequency oscillation between start-up and  
shutdown around the temperature threshold.  
www.austriamicrosystems.com/LDOs/AS1374  
Revision 1.8  
14 - 18