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AS1310-BTDT-27 参数 Datasheet PDF下载

AS1310-BTDT-27图片预览
型号: AS1310-BTDT-27
PDF下载: 下载PDF文件 查看货源
内容描述: 超低静态电流,滞回DC-DC升压转换器 [Ultra Low Quiescent Current, Hysteretic DC-DC Step-Up Converter]
分类和应用: 转换器升压转换器
文件页数/大小: 20 页 / 1271 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1310  
Datasheet - Detailed Description  
8 Detailed Description  
8.1 Hysteretic Boost Converter  
Hysteretic boost converters are so called because comparators are the active elements used to determine on-off timing via current and voltage  
measurements. There is no continuously operating fixed oscillator, providing an independent timing reference. As a result, a hysteretic or  
comparator based converter has a very low quiescent current. In addition, because there is no fixed timing reference, the operating frequency is  
determined by external component (inductor and capacitors) and also the loading on the output.  
Ripple at the output is an essential operating component. A power cycle is initiated when the output regulated voltage drops below the nominal  
value of VOUT (0.99 x VOUT).  
Inductor current is monitored by the control loop, ensuring that operation is always dis-continuous.  
The application circuit shown in Figure 1 will support many requirements. However, further optimization may be useful, and the following i
offered as a guide to changing the passive components to more closely match the end requirement.  
8.1.1 Input Loop Timing  
The input loop consists of the source dc supply, the input capacitor, the main inductor, and the N-channel power switchThe n timing of the N-  
channel switch is determined by a peak current measurement or a maximum on time. In the AS1310, peak current is 400m(typand maximum  
on time is 4.2µs (typ). Peak current measurement ensures that the on time varies as the input voltage varies. This imprts linregulation to the  
converter.  
The fixed on-time measurement is something of a safety feature to ensure thahe poweswitch is never permanently on. The fixed on-time is  
independent of input voltage changes. As a result, no line regulation exists.  
Figure 12. Simplified Boost DCDC Architecture  
L1  
SW2  
VIN  
VOUT  
SW1  
CIN  
COUT  
FB  
RLOAD  
IPK  
GND  
0V  
0V  
On time of the power switch (Fraday’Law) is given by:  
LIPK  
-----------------------------------------------------------------  
TON  
=
sec [volts, amps, ohms, Henry]  
(EQ 1)  
(EQ 2)  
VIN (IPKRSW1 + IPKRL1  
)
Applying Min anMax alues and neglecting the resistive voltage drop across L1 and SW1;  
LMIN IPK _ MIN  
TON _ MIN  
=
=
VIN _ MAX  
LMAX IPK _ MAX  
VIN _ MIN  
TON _ MAX  
(EQ 3)  
www.austriamicrosystems.com/DC-DC_Step-Up/AS1310  
Revision 1.8  
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