AS1153/55
Data Sheet - Package Drawings and Markings
10 Package Drawings and Markings
The AS1155/58 and AS1153/57 are available in a 8-pin SOIC package.
Figure 22. 8-pin SOIC Package Diagram
Table 6. 8-pin SOIC Package Dimensions
SOIC - 8LD
MILLIMETERS
MILLIMETERS
Symbol
Symbol
MIN
0.10
0.36
4.80
3.81
MAX
0.25
0.48
4.98
3.99
MIN
0.25
0.41
1.52
0º
MAX
0.50
1.27
1.72
8º
A1
B
h
L
D
E
A
e
1.27 BSC
ZD
A2
0.53 REF
H
5.80
6.20
1.37
1.57
Note:
1. Lead coplanarity should be 0 to 0.10MM max.
2. Package surface finishing:
Top: Matte (Charmilles #18~30)
All Sides: Matte (Charmilles #18~30)
Bottom: Smooth or Matte (Charmilles #18~30)
3. All dimension excluding Mold Flashes and End Flash from the package body shall not exceed 0.25MM per side (D)
4. Details of PIN #1 identifier are optional, but must be located within the zone indicated.
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