AS1123
Datasheet ꢀ Detailed Description
Serial Interface
Data accesses are made serially via pins SDI and SDO. At each CLK rising edge, the signal present at pin SDI is shifted into the first bit of the
internal shift register and the other bits are shifted ahead of the first bit. The MSB is the first bit to be clocked in. In errorꢀdetection mode the shift
register will latchꢀin the corresponding error data of temperatureꢀ, openꢀ, and shortꢀerror register with each falling edge of LD.
The 16ꢀbit data register will latch the data of the shift register at each rising edge of LD. This data is then used to drive the current generator outꢀ
put drivers to switch on the corresponding LEDs as OEN goes low.
Timing Diagrams
This section contains timing diagrams referenced in other sections of this data sheet.
Figure 9. Normal Mode Timing Diagram
tW(CLK)
50%
50%
50%
CLK
SDI
tSU(D)
tH(D)
50%
50%
SDO
50%
tP1
tW(L)
50%
50%
LD
tSU(L)
tH(L)
OEN
OEN Low = Output Enabled
OUTNx High = Output Off
OUTNx Low = Output On
50%
OUTNx
tP2
Figure 10. Output Delay Timing Diagram
tW(OE)
OEN
50%
50%
tP3
tP3
OUTN0:15
90%
90%
50%
50%
10%
10%
tOR
tOF
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