AS1122
Datasheet ꢀ Detailed Description
PWM scheme of AS1122
The AS1122 uses a scrambled PWM scheme. Meaning the PWM value is divide into supꢀperiods (32 bits wide) and than evenly distributed over
the whole PWM cycle. If the PWM setting can not be divided by 32, the rest is added at the beginning of the PWM cycle.
Figure 39 shows some examples how different PWM settings are distributed over one PWM cycle.
Figure 39. Different PWM Outputs of AS1122
The PWM clock is generated internally and is running with fOSZ (10MHz typ.). For a PWM value of 20 the OUT channel is high for 20 PWMꢀclock
pulses (20 x 100ns) and stays then low for 4076 PWMꢀclock pulses (4076 x 100ns). After one PWM cycle (4096 pulses) the cycle is repeated
endless until the output channels is turned off or updated with new PWM data.
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