AS1122
Datasheet ꢀ Detailed Description
Timing for Cascading of n-devices
With the rising edge of CLKI the data will shifted from SDI into the device. The rising edge of CLKI is shifted through the devices to CLKO. After
a factory fixed highꢀtime (100ns) the falling edge of CLKO is triggered and the data are shifted out via SDO. This ensures a synchronous timing
between CLKO and SDO. The CLK period (frequency) will stay the same only the duty cycle will be changed.
The fixed highꢀtime will vary with +/ꢀ 30%.
Figure 36. Clock Handling with 5MHz Data-Clock
Figure 37. Clock Handling with 2MHz Data-Clock
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