AS1112
Datasheet - Detailed Description
Figure 10. Dot Correction Data Input Timing Diagram
Dot Correction Mode
Data Input Cycle n
Dot Correction Mode
Data Input Cycle n +1
VCC
MODE
GND
DCn-1
LSB
DCn
MSB
DCn
MSB-1
DCn
MSB-2
DCn
LSB+1
DCn
LSB
DCn+1
MSB
DCn+1
MSB-1
SDI
tSU0
tWH0
2
CLK
1
1
95
96
1
2
tWL0
DCn-1
MSB
DCn-1
MSB-1
DCn-1
MSB-2
DCn-1
LSB+1
DCn-1
LSB
DCn
DCn
MSB-1 MSB-2
DCn
MSB
tWH2
SDO
LD
tSU1
tH1
Setting Greyscale Brightness
The brightness of each channel output can be adjusted using a 12 bits-per-channel PWM control scheme which results
in 4096 brightness steps, from 0% to 100% brightness. The brightness level for each output is calculated as:
GSn
%Brightness=
x 100
(EQ 4)
4095
Where:
GSn is the programmed greyscale value for OUTn (GSn = 0 to 4095);
n = 0 to 15 greyscale data for all outputs.
The device powers up with the following default seetings: GS = 4095 and DC = 63.
The input shift register shifts greyscale data into the greyscale register for all channels simultaneously. The complete
greyscale data format consists of 16 x 12 bit words, which forms a 192-bit wide data packet (see Figure 11).
Note: The data packet must be clocked in with the MSB first.
Figure 11. Greyscale Data Packet Format
MSB
191
LSB
0
180
179
12
11
...
...
...
GS15.11
GS15.0 GS14.11
GS1.0
GS0.11
GS0.0
GS OUT15
GS OUT14:GS OUT1
GS OUT0
When pin MODE is tied to GND, the AS1112 enters greyscale data input mode. The device switches the input shift reg-
ister to 192-bit width. After all data is clocked in, the rising edge of the LD signal latches the data into the greyscale reg-
ister (see Figure 12).
All greyscale data in the input shift register is replaced with status information data (SID) after latching into the grey-
scale register.
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