AS1109
Data Sheet - Detailed Description
Serial Interface
Data accesses are made serially via pins SDI and SDO. At each CLK rising edge, the signal present at pin SDI is
shifted into the first bit of the internal shift register and the other bits are shifted ahead of the first bit. The MSB is the
first bit to be clocked in. In error-detection mode the shift register will latch-in the corresponding error data of tempera-
ture-, open-, and short-error register with each falling edge of LD.
The 8-bit data register will latch the data of the shift register at each rising edge of LD. This data is then used to drive
the current generator output drivers to switch on the corresponding LEDs as OEN goes low.
Timing Diagrams
This section contains timing diagrams referenced in other sections of this data sheet.
Figure 10. Normal Mode Timing Diagram
tW(CLK)
50%
50%
50%
CLK
SDI
tSU(D)
tH(D)
50%
50%
SDO
50%
tP1
tW(L)
LD
50%
50%
tSU(L)
tH(L)
OEN
OEN Low = Output Enabled
OUTNx High = Output Off
OUTNx Low = Output On
OUTNx
50%
tP2
Figure 11. Output Delay Timing Diagram
tW(OE)
90%
OEN
50%
50%
tP3
tP3
90%
50%
50%
OUTN0
10%
10%
tOR
tOF
tSTAG
50%
tSTAG
50%
OUTN1
OUTN7
7XtSTAG
7XtSTAG
50%
50%
www.austriamicrosystems.com
Revision 1.18
9 - 26
AMSCO [ AMS(艾迈斯) ]
