AS1109
Data Sheet - Package Drawings and Markings
10 Package Drawings and Markings
The device is available in an 16-pin SOIC-150 package.
Figure 25. 16-pin SOIC-150 Package
Notes:
Symbol
Min
0.10
0.36
0.19
9.80
3.81
Max
0.25
0.46
0.25
9.98
3.99
1. Lead coplanarity should be 0 to 0.10mm (.004”) max.
2. Package surfacing:
A1
B
a. Top: matte (charmilles #18- 30).
C
D
E
b. All sides: matte (charmilles #18- 30).
c. Bottom: smooth or matte (charmilles #18- 30).
3. All dimensions excluding mold flashes and end flash from the
package body shall not exceed 0.25mm (.010”) per side (D).
e
1.27 BSC
H
h
5.80
0.25
0.41
1.52
0º
6.20
0.50
1.27
1.72
8º
4. Detail of pin #1 identifier are optional but must be located
within the zone indicated.
L
5. Dimensions are in millimeters.
A
α
ZD
A2
0.51 REF
1.37
1.57
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