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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS3525-A/-B C22O22  
Data Sheet, Confidential  
7.4.18  
Interrupt Generation  
7.4.18.1 General  
All interrupt sources can get enabled or disabled by corresponding bits in the 3 IRQ-bytes. By default no IRQ source is enabled.  
The IRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD_2 register  
(0x27). Default state is open drain and active_low.  
7.4.18.2 IRQ Source Interpretation  
There are 3 different modules to process interrupt sources:  
7.4.18.3 LEVEL  
The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled  
7.4.18.4 EDGE  
The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.  
7.4.18.5 STATUS CHANGE  
The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source. The IRQ  
stays active until the corresponding interrupt register gets read.  
7.4.18.6 De-bouncer  
There is a de-bounc function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or unplug, a de-  
bounce time of 512ms/256ms/128ms can be selected by 2 bits in the IRQ_ENRD2 register (0x27h).  
Table 145 First Interrupt Register  
Name  
Base  
Default  
0x00  
IRQ_ENRD_0  
I2C audio master  
First Interrupt Register  
Please be aware that writing to this register will enable/disable the corresponding  
interrupts, while with reading you get the actual interrupt status and will clear the  
register at the same time. It is not possible to read back the interrupt enable/disable  
settings. This register is reset at a DVDD-POR.  
Offset: 0x25  
Bit  
Bit Name  
Default  
Access  
Bit Description  
7
CHG_tmphigh  
(level)  
0
x
0
W
battery over-temperature interrupt setting  
0: disable  
1: enable  
The interrupt must not be enabled if the charger block and  
battery temperature supervision is disabled  
Battery over-temperature interrupt reading  
0: battery temperature below 55°C  
1: battery temperature was too high and the charger was  
turned off. The charger will be turned on again, when the  
temperature gets below 50°C  
R
6
CHG_endofch  
(edge)  
W
Battery end of charge interrupt setting  
0: disable  
1: enable  
The interrupt must not be enabled if the charger block is  
disabled  
x
x
R
R
Battery end of charge interrupt reading  
0: battery charging in progress  
1: charging is complete, turn charger off  
To check end of charge again the charger has to be turned on.  
0: no charger input source connected  
1: charger input source connected, also valid if charger is  
connected during wakeup  
5
CHG_status  
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www.austriamicrosystems.com Revision 1.13  
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