AS3525-A/-B C22O22
Data Sheet, Confidential
7.4.4.4 Register Settings
Table 106 CVDD / DCDC3 Register
Name
Base
Default
0x00
CVDD / DCDC 3
I2C audio master
Charge Pump and 3V DCDC Register
This register is reset at a DVDD-POR.
Offset: 0x21
Bit
Bit Name
CP_SW
Default
Access
Bit Description
7
0
R/W
charge pump / length regulator switch margin reduction
0: margin set to 200/300 mV
1: margin reduced to 150/225 mV (automatic switching to
length regulator is done “later”, at a lower input voltage)
6
5
CP_on
0
0
R/W
R
0: normal operation
1: keeps Mode 3 charge pump always on
Please note that bit 2 = “0”, overrides bit 6.
Core voltage generation mode
LREG_CPnot
0: CP is working
1: LREG is working
W
For production testing purpose only, in normal application
mode this bit must always be written with “0”.
4:3
DCDC3p
00
R/W
DCDC3 Vout programming (BVDD)
00: 3.6V
01: 3.2V
10: 3.1V
11: 3.0V
2
LREG_off
CVDDp
0
R/W
R/W
0: keeps Mode2 (length regulator always on)
1: normal operation
CVDD trimming:
00: 1.2V
1:0
00
01: 1.15V
10: 1.10V
11: 1.05V
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