AMS73CAG01808RA
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff.
The Mode Register 1 is written by asserting low on CS, RAS, CAS, WE, high on BA0, low on BA1 and BA2,
while controlling the states of address pins according to the table below.
A
13
A
12
A
10
A
11
BA
2
BA
0
1
BA
1
0
A
9
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
A
8
Address Field
Mode Register 1
1
0*1
0*1
0
1
*
*
0
Rtt_Nom
Rtt_Nom
Rtt_Nom
Qoff TDQS
AL
Level
D.I.C
D.I.C DLL
A9 A6 A2
Rtt_Nom *3
A11 TDQS enable
A0 DLL Enable
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
ODT disabled
RZQ/4
0
1
Disabled
Enabled
0
1
Enable
Disable
RZQ/2
RZQ/6
RZQ/12*4
A7
0
Write leveling enable
Disabled
RZQ/8*4
Reserved
Reserved
1
0
1
1
1
1
1
0
1
1
Enabled
Note : RZQ = 240 ohms
Additive Latency
0 (AL disabled)
CL-1
A4
0
A3
0
*
3: In Write leveling Mode (MR1[bit7] = 1)
with MR1[bit12] = 1, all RTT_Nom settings
are allowed; in Write Leveling Mode
(MR1[bit7] = 1) with MR1[bit12] = 0, only
RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
0
1
1
0
CL-2
1
1
Reserved
*
4: If RTT_Nom is used during Writes,
only the values RZQ/2,RZQ/4 and RZQ/6
are allowed.
*2
A12
0
Qoff
A5 A1 Output Driver Impedance Control
Output buffer enabled
0
0
1
1
0
1
0
1
RZQ/6
RZQ/7
Output buffer disabled *2
1
*2: Outputs disabled - DQs, DQSs, DQSs.
RZQ/TBD
RZQ/TBD
BA1
BA0
MRS mode
MR0
Note : RZQ = 240 ohms
0
0
1
1
0
1
0
1
MR1
MR2
MR3
* 1 : BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
AMS73CAG01808RA Rev. 1.0 December 2010
8
AMS [ Advanced Monolithic Systems Ltd ]
