AMS73CAG01808RA
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It con-
trols burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various appli-
cations. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
Address Field
BA2
BA1
BA0
A
13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*1
Mode Register 0
A0
0*1
DLL TM
CAS Latency
RBT
0
0
PPD
WR
BL
CL
A3
0
Read Burst Type
Nibble Sequential
Interleave
A1
0
BL
mode
Normal
Test
A7
A8
0
DLL Reset
No
0
1
0
1
8 (Fixed)
4 or 8(on the fly)
4 (Fixed)
0
1
1
0
1
Yes
1
1
Reserved
DLL Control for
Precharge PD
Write recovery for autoprecharge
A12
CAS Latency
A6 A5 A4
A11
0
A10
0
A9
0
WR(cycles)
Reserved
A2
0
Latency
0
1
Slow exit (DLL off)
Fast exit (DLL on)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Reserved
5*2
6*2
0
0
1
0
5
6
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
7
7*2
BA1
BA0
MRS mode
MR0
0
8
0
0
1
1
0
1
0
1
8*2
0
9
MR1
10*2
0
10
MR2
12*2
11(Optional for
DDR3-1600)
MR3
1
1
1
0
Reserved
*1 : BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.
*2 : WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the
next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or
larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
AMS73CAG01808RA Rev. 1.0 December 2010
7
AMS [ Advanced Monolithic Systems Ltd ]
