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LP61L1024V-15 参数 Datasheet PDF下载

LP61L1024V-15图片预览
型号: LP61L1024V-15
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8位3.3V高速低VCC CMOS SRAM [128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 16 页 / 180 K
品牌: AMICC [ AMIC TECHNOLOGY ]
 浏览型号LP61L1024V-15的Datasheet PDF文件第1页浏览型号LP61L1024V-15的Datasheet PDF文件第2页浏览型号LP61L1024V-15的Datasheet PDF文件第3页浏览型号LP61L1024V-15的Datasheet PDF文件第4页浏览型号LP61L1024V-15的Datasheet PDF文件第6页浏览型号LP61L1024V-15的Datasheet PDF文件第7页浏览型号LP61L1024V-15的Datasheet PDF文件第8页浏览型号LP61L1024V-15的Datasheet PDF文件第9页  
LP61L1024  
Truth Table  
Mode  
CE2  
I/O Operation  
Supply Current  
CE1  
H
OE  
X
WE  
X
X
L
High Z  
High Z  
High Z  
DOUT  
ISB, ISB1  
ISB, ISB2  
ICC1  
Standby  
X
X
X
Output Disable  
Read  
L
H
H
H
H
L
H
L
H
ICC1  
Write  
L
X
L
DIN  
ICC1  
Note: X = H or L  
Capacitance (TA = 25°C, f = 1.0MHz)  
Symbol  
CIN*  
Parameter  
Min.  
Max.  
Unit  
pF  
Conditions  
VIN = 0V  
Input Capacitance  
8
CI/O*  
Input/Output Capacitance  
10  
pF  
VI/O = 0V  
* These parameters are sampled and not 100% tested.  
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V)  
LP61L1024-12  
LP61L1024-15  
Symbol  
Parameter  
Unit  
Min.  
Max.  
Min.  
Max.  
Read Cycle  
tRC  
tAA  
Read Cycle Time  
Address Access Time  
12  
-
-
15  
-
-
ns  
ns  
ns  
12  
12  
15  
15  
tACE1  
Chip Enable Access Time  
-
-
CE1  
CE2  
tACE2  
tOE  
-
-
12  
7
-
-
15  
9
ns  
ns  
ns  
Output Enable to Output Valid  
Chip Enable to Output in Low Z  
tCLZ1  
3
-
5
-
CE1  
CE2  
tCLZ2  
tOLZ  
3
2
-
-
-
5
2
-
-
-
ns  
ns  
ns  
Output Enable to Output in Low Z  
Chip Disable to Output in High Z  
tCHZ1  
7
10  
CE1  
CE2  
tCHZ2  
tOHZ  
tOH  
-
7
7
-
-
10  
9
ns  
ns  
ns  
Output Disable to Output in High Z  
Output Hold from Address Change  
2
3
2
5
-
(August, 2002, Version 2.1)  
4
AMIC Technology, Inc.