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A62L256M-70LLU 参数 Datasheet PDF下载

A62L256M-70LLU图片预览
型号: A62L256M-70LLU
PDF下载: 下载PDF文件 查看货源
内容描述: 32K ×8位的低电压CMOS SRAM [32K X 8 BIT LOW VOLTAGE CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 14 页 / 148 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A62L256 Series  
AC Characteristics (TA = 0°C to +70°C or -40ºC to +85ºC)  
A62L256-55LL/LLU  
(VCC = 3.0V to 3.6V)  
A62L256-70LL/LLU  
(VCC = 2.7V to 3.6V)  
Symbol  
Parameter  
Unit  
Min.  
Max.  
Min.  
Max.  
Read Cycle  
tRC  
Read Cycle Time  
55  
-
-
70  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address Access Time  
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
Chip Enable Access Time  
-
-
Output Enable to Output Valid  
Chip Enable to Output in Low Z  
Output Enable to Output in Low Z  
Chip Disable to Output in High Z  
Output Disable to Output in High Z  
Output Hold from Address Change  
-
-
tCLZ  
10  
5
-
10  
5
tOLZ  
-
-
tCHZ  
tOHZ  
tOH  
20  
20  
-
-
25  
25  
-
-
-
5
10  
Write Cycle  
tWC  
Write Cycle Time  
55  
50  
0
-
-
70  
60  
0
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCW  
Chip Enable to End of Write  
Address Set up Time  
tAS  
-
-
tAW  
Address Valid to End of Write  
Write Pulse Width  
50  
40  
0
-
60  
50  
0
-
tWP  
-
-
tWR  
Write Recovery Time  
-
-
tWHZ  
tDW  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
-
25  
-
-
25  
-
25  
0
30  
0
tDH  
-
-
tOW  
5
-
5
-
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not  
referred to output voltage levels.  
PRELIMINARY  
(November, 2001, Version 1.4)  
6
AMIC Technology, Inc.