A43L2616B
Page Read & Write Cycle at Same Bank @Burst Length=4
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CLOCK
CKE
High
CS
tRCD
RAS
CAS
*Note 2
ADDR
BA0
Ra
Ca
Cb
Cc
Cd
BA1
A10/AP
WE
Ra
tRDL
tCDL
*Note 2
*Note1
*Note3
DQM
DQ
(CL=2)
Qb2
Qb1
Qa0
Qa1
Qb0
Qa1
Qb1
Qb0
Dc0
Dc0
Dc1
Dd0
Dd0
Dd1
DQ
(CL=3)
Qa0
Dc1
Dd1
Row Active
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
(December, 2009, Version 1.3)
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AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
