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A43L0632G-95I 参数 Datasheet PDF下载

A43L0632G-95I图片预览
型号: A43L0632G-95I
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位×4银行同步DRAM [1M X 16 Bit X 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 42 页 / 502 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A43L2616B  
Simplified Truth Table  
Command  
CKEn-1 CKEn CS RAS  
DQM BA0 A10 A9~A0, Notes  
CAS  
L
WE  
L
BA1 /AP  
A11  
Register  
Mode Register Set  
Auto Refresh  
1,2  
H
H
X
L
L
X
X
OP CODE  
3
3
3
Refresh  
H
L
L
L
L
L
H
H
X
Entry  
Self  
H
H
Refresh  
Exit  
L
H
X
X
X
X
H
L
X
L
X
H
X
H
3
4
Bank Active & Row Addr.  
H
V
V
Row Addr.  
Read &  
Column Addr.  
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
L
Column  
Addr.  
4
H
X
L
H
L
H
X
H
L
4,5  
4
Write &  
Column  
Addr.  
H
H
X
X
L
L
H
H
L
L
L
X
X
V
Column Addr.  
H
4,5  
Burst Stop  
Precharge  
H
X
Bank Selection  
Both Banks  
V
X
L
H
X
L
L
H
L
X
X
H
L
H
X
L
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry  
H
L
L
H
L
X
X
X
Clock Suspend or  
Active Power Down  
X
X
Exit  
Entry  
H
H
L
Precharge Power Down Mode  
Exit  
L
H
H
H
X
X
V
X
H
DQM  
X
X
6
L
H
X
H
X
No Operation Command  
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)  
Note : 1. OP Code: Operand Code  
A0~A11, BA0, BA1: Program keys. (@MRS)  
2. MRS can be issued only at both banks precharge state.  
A new command can be issued after 2 clock cycle of MRS.  
3. Auto refresh functions as same as CBR refresh of DRAM.  
The automatical precharge without Row precharge command is meant by “Auto”.  
Auto/Self refresh can be issued only at both precharge state.  
4. BA0, BA1 : Bank select address.  
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.  
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.  
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.  
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.  
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read write command cannot be issued.  
Another bank read write command can be issued at every burst length.  
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but  
masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)  
(December, 2009, Version 1.3)  
8
AMIC Technology, Corp.