A43L2616B
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BA0, BA1
A11, A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 1)
(Note 2)
Test Mode
Type
CAS Latency
A6 A5 A4 Latency
Burst Type
Burst Length
A8 A7
A3
Type
A2 A1 A0
BT=0
BT=1
0
0
1
1
0
1
0
1
Mode Register Set
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
-
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Vendor
Use
2
Only
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
256(Full) Reserved
Write Burst Length
Length
A9
0
Burst
1
Single Bit
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200μs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
(December, 2009, Version 1.3)
9
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
