A43E16161
8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4)
CLK
2) Write Burst Stop (BL=8)
CLK
CMD
CMD
WR
PRE
WR
STOP
DQM
DQ
D0
D1
D2
D3
DQ
D1
D0
D2
Note 1
t
RDL
t
BDL (note 2)
3) Read Interrupted by Precharge (BL=4)
CLK
4) Read Burst Stop (BL=4)
CLK
CMD
CMD
DQ(CL2)
DQ(CL3)
RD
RD
PRE
Q0
STOP
Q0
Note 3
1
Note 3
1
DQ(CL2)
DQ(CL3)
Q1
Q0
Q1
Q0
2
2
Q1
Q1
9. MRS
Mode Register Set
CLK
Note 4
PRE
MRS ACT
1CLK
CMD
t
RP
Note : 1. tRDL : 2CLK, Last Data in to Row Precharge.
2. tBDL : 1CLK, Last Data in to Burst Stop Delay.
3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
PRELIMINARY (August, 2005, Version 0.0)
18
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
