A43E06161
Read & Write Cycle with Auto Precharge I @Burst Length=4
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CLOCK
CKE
High
CS
RAS
CAS
RAa
RAa
RBb
RBb
CAa
CBb
ADDR
BA
A10/AP
WE
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Auto Precharge
Start Point
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
(B-Bank)
Row Active
(B-Bank)
: Don't care
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode)
PRELIMINARY (July, 2005, Version 0.1)
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AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
