A26E001A
Block Diagram
VCC
GND
RAM
A0 - A14
WE
OE
A0-A14
A15 - A17
ADDRESS
BUFFER
RAMCE
D0-D7
D0-D7
D0 - D7
DATA
BUFFER
CIRCUIT
WE
OE
A0-A14
ROMCE
A15-A17
WE
OE
CONTROL
CIRCUIT
ROM
RAMCE
ROMCE
Truth Table
Mode
Standby
D0 - D7
Supply Current
ROMCE
RAMCE
OE
X
WE
X
H
L
H
H
H
L
High Z
High Z
DOUT
ISB, ISB1
ICCR
Output Disable
ROM Read
H
L
X
L
X
ICCR
Output Disable
SRAM Read
SRAM Write
H
H
H
H
L
H
High Z
DOUT
ICCS
L
H
ICCS
L
X
L
DIN
ICCS
Notes:
1. X = H or L
2. A15 - A17 are only valid for ROM.
3. In case that and
are "L" at the same time, both ROM and SRAM will be disabled.
RAMCE
ROMCE
(November, 1998, Version 2.1)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
