A25LQ080 Series
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input(s) IO0 (IO1, IO2, IO3) is (are) sampled on the
Read Status Register (RDSR) or Release from Deep
Power-down, Read Device Identification and Read Electronic
Signature (RES) instruction, the shifted-in instruction se-
first rising edge of Serial Clock (C) after Chip Select ( ) is
S
quence is followed by a data-out sequence. Chip Select (
)
S
driven Low. Then, the one-byte instruction code must be
shifted in to the device, most significant bit first, on Serial Data
Input(s) IO0 (IO1, IO2, IO3), each bit being latched on the rising
edges of Serial Clock (C).
can be driven High after any bit of the data-out sequence is
being shifted out.
In the case of a Page Program (PP), Program OTP (POTP),
Dual Input Fast Program (DIFP), Quad Input Fast Program
(QIFP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR), Write Enable (WREN), Write
Disable (WRDI) or Deep Power-down (DP) instruction, Chip
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by dummy bytes (don’t
care), or by a combination or none.
Select ( ) must be driven High exactly at a byte boundary,
S
otherwise the instruction is rejected, and is not executed. That
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Data Bytes at Higher Speed
by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data
Bytes at Higher Speed by Dual Input and Dual Output
(FAST_READ_DUAL_INPUT_OUTPUT) , Read Data Bytes at
Higher Speed by Quad Output (FAST_READ_QUAD
_OUTPUT), Read Data Bytes at Higher Speed by Quad Input
and Quad Output (FAST_READ_QUAD_INPUT_OUTPUT),
Read OTP (ROTP), Read Identification (RDID), Read
Electronic Manufacturer and Device Identification (REMS),
is, Chip Select ( ) must driven High when the number of
S
clock pulses after Chip Select ( ) being driven Low is an
S
exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
(April, 2016, Version 1.0)
10
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
