A25L80P
Figure 16. Release from Deep Power-down (RES) Instruction Sequence
S
tRES1
1
3
0
2
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode Stand-by Mode
Power-down mode, though, the transition to the Stand-by
S
Driving Chip Select ( ) High after the 8-bit instruction byte has
been received by the device, but before the whole of the 8-bit
Electronic Signature has been transmitted for the first time (as
shown in Figure 16.), still insures that the device is put into
Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power
mode is immediate. If the device was previously in the Deep
S
Power mode is delayed by tRES1, and Chip Select ( ) must
remain High for at least tRES1 (max), as specified in AC
Characteristics Table. Once in the Stand-by Power mode, the
device waits to be selected, so that it can receive, decode and
execute instructions.
PRELIMINARY (May 2005, Version 0.0)
21
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
