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A25L16PN-UF 参数 Datasheet PDF下载

A25L16PN-UF图片预览
型号: A25L16PN-UF
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 16MX1, PDSO16, 0.300 INCH, LEAD FREE, SOP-16]
分类和应用: 时钟光电二极管内存集成电路
文件页数/大小: 37 页 / 582 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L16P Series  
Fast Read Dual Input-Output (BBh)  
The Fast Read Dual Input-Output (BBh) instruction is similar to  
the Fast_Read (0Bh) instruction except the data is input and  
output on two pins, DO and DIO, instead of just DO. This  
allows data to be transferred from the A25L16P at twice the  
rate of standard SPI devices.  
(See AC Characteristics). This is accomplished by adding four  
“dummy” clocks after the 24-bit address as shown in figure 11.  
The dummy clocks allow the device’s internal circuits additional  
time for setting up the initial address. The input data during the  
dummy clocks is “don’t care”. However, the DIO and DO pins  
should be high-impedance prior to the falling edge of the first  
data out clock.  
Similar to the Fast Read instruction, the Fast Read Dual Output  
instruction can operate at the highest possible frequency of fC  
Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence  
S
6
0
1
2
3
4
5
7
8
9 10  
16 17 18 19  
C
DIO  
DO  
Instruction  
24-Bit Address  
22  
18  
4
2
3
0
1
20  
6
MSB  
High Impedance  
23  
19  
5
7
21  
S
C
20 21 22 23 24 25 26 27 28  
Dummy  
29 30 31 32 33 34 35  
DIO switches from input to output  
Byte  
3
2
1
0
6
4
2
0
6
4
2
0
6
4
2
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
DIO  
DO  
3
1
3
7
5
3
1
5
7
5
7
7
MSB  
MSB  
MSB  
MSB  
Data Out 2  
Data Out 3  
Data Out 4  
Data Out 5  
Data Out 1  
Note: Address bits A23 to A21 are Don’t Care.  
PRELIMINARY (March, 2006, Version 0.2)  
16  
AMIC Technology Corp.  
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