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A25L080Q4-UFG 参数 Datasheet PDF下载

A25L080Q4-UFG图片预览
型号: A25L080Q4-UFG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mbit的低电压,串行闪存的100MHz统一4KB扇区 [16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors]
分类和应用: 闪存
文件页数/大小: 43 页 / 681 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L016 Series  
OPERATING FEATURES  
Page Programming  
WIP bit. The Write In Progress (WIP) bit indicates whether  
the memory is busy with a Write Status Register, Program or  
Erase cycle.  
To program one data byte, two instructions are required: Write  
Enable (WREN), which is one byte, and a Page Program (PP)  
sequence, which consists of four bytes plus data. This is  
followed by the internal Program cycle (of duration tPP).  
To spread this overhead, the Page Program (PP) instruction  
allows up to 256 bytes to be programmed at a time (changing  
bits from 1 to 0), provided that they lie in consecutive  
addresses on the same page of memory.  
WEL bit. The Write Enable Latch (WEL) bit indicates the  
status of the internal Write Enable Latch.  
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits  
are non-volatile. They define the size of the area to be  
software protected against Program and Erase instructions.  
Sector Erase, Block Erase, and Chip Erase  
SRWD bit. The Status Register Write Disable (SRWD) bit is  
The Page Program (PP) instruction and Dual Input Fast  
Program (DIFP) instruction allow bits to be reset from 1 to 0.  
Before this can be applied, the bytes of memory need to have  
been erased to all 1s (FFh). This can be achieved, a sector at  
a time, using the Sector Erase (SE) instruction, a block at a  
time, using the Block Erase (BE) instruction, or throughout the  
entire memory, using the Chip Erase (CE) instruction. This  
starts an internal Erase cycle (of duration tSE, tBE, or tCE).  
The Erase instruction must be preceded by a Write Enable  
(WREN) instruction.  
operated in conjunction with the Write Protect ( ) signal.  
W
The Status Register Write Disable (SRWD) bit and Write  
Protect ( ) signal allow the device to be put in the Hardware  
W
Protected mode. In this mode, the non-volatile bits of the  
Status Register (SRWD, BP2, BP1, BP0) become read-only  
bits.  
Protection Modes  
The environments where non-volatile memory devices are  
used can be very noisy. No SPI device can operate correctly  
in the presence of excessive noise. To help combat this, the  
A25L016 boasts the following data protection mechanisms:  
„ Power-On Reset and an internal timer (tPUW) can provide  
protection against inadvertent changes while the power  
supply is outside the operating specification.  
„ Program, Erase and Write Status Register instructions are  
checked that they consist of a number of clock pulses that  
is a multiple of eight, before they are accepted for  
execution.  
Polling During a Write, Program or Erase Cycle  
A further improvement in the time to Write Status Register  
(WRSR), Program (PP) or Erase (SE, BE, or CE) can be  
achieved by not waiting for the worst case delay (tW, tPP, tSE  
,
t
BE, tCE). The Write In Progress (WIP) bit is provided in the  
Status Register so that the application program can monitor  
its value, polling it to establish when the previous Write cycle,  
Program cycle or Erase cycle is complete.  
„ All instructions that modify data must be preceded by a  
Write Enable (WREN) instruction to set the Write Enable  
Latch (WEL) bit. This bit is returned to its reset state by  
the following events:  
Active Power, Stand-by Power and Deep  
Power-Down Modes  
When Chip Select ( ) is Low, the device is enabled, and in  
S
the Active Power mode.  
- Power-up  
- Write Disable (WRDI) instruction completion  
- Write Status Register (WRSR) instruction completion  
- Page Program (PP) instruction completion  
- Sector Erase (SE) instruction completion  
- Block Erase (BE) instruction completion  
When Chip Select ( ) is High, the device is disabled, but  
S
could remain in the Active Power mode until all internal cycles  
have completed (Program, Erase, Write Status Register). The  
device then goes in to the Stand-by Power mode. The device  
consumption drops to ICC1.  
The Deep Power-down mode is entered when the specific  
instruction (the Deep Power-down Mode (DP) instruction) is  
executed. The device consumption drops further to ICC2. The  
device remains in this mode until another specific instruction  
(the Release from Deep Power-down Mode and Read  
Electronic Signature (RES) instruction) is executed.  
All other instructions are ignored while the device is in the  
Deep Power-down mode. This can be used as an extra  
software protection mechanism, when the device is not in  
active use, to protect the device from inadvertent Write,  
Program or Erase instructions.  
- Chip Erase (CE) instruction completion  
„ The Block Protect (BP2, BP1, BP0) bits allow part of the  
memory to be configured as read-only. This is the  
Software Protected Mode (SPM).  
„ The Write Protect ( ) signal allows the Block Protect  
W
(BP2, BP1, BP0) bits and Status Register Write Disable  
(SRWD) bit to be protected. This is the Hardware  
Protected Mode (HPM).  
„ In addition to the low power consumption feature, the  
Deep Power-down mode offers extra software protection  
from inadvertent Write, Program and Erase instructions, as  
all instructions are ignored except one particular instruction  
(the Release from Deep Power-down instruction).  
Status Register  
The Status Register contains a number of status and control  
bits that can be read or set (as appropriate) by specific  
instructions.  
(March, 2012, Version 2.0)  
5
AMIC Technology Corp.  
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