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A25L080 Series
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (DIO) is sampled on the first rising edge of
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block
Erase (BE), Chip Erase (CE), Write Status Register (WRSR),
Write Enable (WREN), Write Disable (WRDI) or Deep
Serial Clock (C) after Chip Select ( ) is driven Low. Then, the
S
Power-down (DP) instruction, Chip Select ( ) must be driven
S
High exactly at a byte boundary, otherwise the instruction is
one-byte instruction code must be shifted in to the device,
most significant bit first, on Serial Data Input (DIO), each bit
being latched on the rising edges of Serial Clock (C).
rejected, and is not executed. That is, Chip Select ( ) must
S
driven High when the number of clock pulses after Chip Select
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Status Register (RDSR) or
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
(
) being driven Low is an exact multiple of eight.
S
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
Select ( ) can be driven High after any bit of the data-out
S
Table 3. Instruction Set
One-byte
Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
Instruction
WREN
Description
Write Enable
Write Disable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
06h
04h
05h
01h
03h
0Bh
0
0
0
0
3
3
0
0
0
0
0
1
0
WRDI
0
RDSR
Read Status Register
Write Status Register
1 to ∞
1
WRSR
READ
Read Data Bytes
1 to ∞
1 to ∞
FAST_READ
Read Data Bytes at Higher Speed
FAST_READ_DUAL
_OUTPUT
Read Data Bytes at Higher Speed by
Dual Output (1)
00111011
10111011
3Bh
BBh
3
1
1 to ∞
1 to ∞
FAST_READ_DUAL
_INPUT-OUTPUT
Read Data Bytes at Higher Speed by
Dual Input and Dual Output (1)
3(2)
1(2)
PP
Page Program
Sector Erase
0000 0010
0010 0000
1101 1000
1100 0111
1011 1001
1001 1111
02h
20h
D8h
C7h
B9h
9Fh
3
3
3
0
0
0
0
0
0
0
0
0
1 to 256
SE
0
BE
Block Erase
0
0
CE
Chip Erase
DP
Deep Power-down
Read Device Identification
0
RDID
1 to ∞
Read Electronic Manufacturer & Device
Identification
REMS
1001 0000
90h
1(3)
2
1 to ∞
Release from Deep Power-down, and
Read Electronic Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-down
0
Note: (1) DIO = (D6, D4, D2, D0)
DO = (D7, D5, D3, D1)
(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)
DO = (A23, A21, A19, …….., A7, A5, A3, A1)
(3) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first
(March, 2012, Version 1.6)
8
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
