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A25L080 Series
SPI MODES
falling edge of Serial Clock (C).
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 1. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA)
SDI
SCK
= (0, 0) or (1, 1)
C
DO DIO
C
DO DIO
C
DO DIO
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
W HOLD
S
W HOLD
S
W HOLD
Note: The Write Protect ( ) and Hold (
W
) signals should be driven, High or Low as appropriate.
HOLD
Figure 2. SPI Modes Supported
CPOL CPHA
0
1
0
1
C
C
DIO
DO
MSB
MSB
(March, 2012, Version 1.6)
4
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
