A25L80P
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising edge of
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP)
Serial Clock (C) after Chip Select ( ) is driven Low. Then, the
S
instruction, Chip Select ( ) must be driven High exactly at a
S
byte boundary, otherwise the instruction is rejected, and is not
one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
executed. That is, Chip Select ( ) must driven High when the
S
The instruction set is listed in Table 3.
number of clock pulses after Chip Select ( ) being driven Low
S
is an exact multiple of eight.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Status Register (RDSR) or
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
Select ( ) can be driven High after any bit of the data-out
S
Table 3. Instruction Set
Address
Bytes
Dummy
Bytes
Instruction
Description
Write Enable
One-byte Instruction Code
Data Bytes
WREN
WRDI
RDSR
WRSR
READ
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
1001 1111
06h
04h
05h
01h
03h
0Bh
02h
D8h
C7h
B9h
9Fh
0
0
0
0
3
3
3
3
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
1 to ∞
1
1 to ∞
1 to ∞
1 to 256
0
FAST_READ Read Data Bytes at Higher Speed
PP
SE
Page Program
Sector Erase
BE
Bulk Erase
0
DP
Deep Power-down
Read Device Identification
0
RDID
1 to 3
Release from Deep Power-down,
and Read Electronic Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-down
0
PRELIMINARY (May 2005, Version 0.0)
8
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
