A25L80P
Table 1. Protected Area Sizes
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
All sectors1 (sixteen sectors: 0 to 15)
Upper sixteenth (sector 15)
Lower fifteen-eighths (fifteen sectors: 0 to 14)
Upper eighth (two sectors: 14 and 15)
Upper quarter (four sectors: 12 to 15)
Upper half (eight sectors: 8 to 15)
All sectors (eight sectors: 0 to 15)
All sectors (eight sectors: 0 to 15)
All sectors (eight sectors: 0 to 15)
Lower seven-eights (fourteen sectors: 0 to 13)
Lower three-quarters (twelve sectors: 0 to 11)
Lower half (eight sectors: 0 to 7)
none
none
none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Hold Condition
(C) next goes Low. This is shown in Figure 3.
During the Hold condition, the Serial Data Output (Q) is high
impedance, and Serial Data Input (D) and Serial Clock (C) are
Don’t Care.
The Hold (
) signal is used to pause any serial
HOLD
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not terminate
any Write Status Register, Program or Erase cycle that is
currently in progress.
Normally, the device is kept selected, with Chip Select (
)
S
To enter the Hold condition, the device must be selected, with
driven Low, for the whole duration of the Hold condition. This is
to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
Chip Select ( ) Low.
S
The Hold condition starts on the falling edge of the Hold
If Chip Select ( ) goes High while the device is in the Hold
S
condition, this has the effect of resetting the internal logic of the
device. To restart communication with the device, it is
(
) signal, provided that this coincides with Serial Clock
HOLD
(C) being Low (as shown in Figure 3.).
The Hold condition ends on the rising edge of the Hold (
)
HOLD
necessary to drive Hold (
) High, and then to drive Chip
HOLD
signal, provided that this coincides with Serial Clock (C) being
Low.
Select ( ) Low. This prevents the device from going back to
S
If the falling edge does not coincide with Serial Clock (C) being
Low, the Hold condition starts after Serial Clock (C) next goes
Low. Similarly, if the rising edge does not coincide with Serial
Clock (C) being Low, the Hold condition ends after Serial Clock
the Hold condition.
Figure 3. Hold Condition Activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
PRELIMINARY (May 2005, Version 0.0)
6
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
