A25LQ080 Series
High Performance Mode (A3h)
The High Performance Mode (HPM) instruction can be
executed prior to Dual or Quad I/O instructions if chip is
operated at high frequencies. This instruction allows
pre-charging of internal charge pumps so the voltages
required for accessing the Flash memory array are readily
available. The instruction sequence includes the A3h
instruction code followed by three dummy byte clocks shown
in Fig.28. After the HPM instruction is executed, the device
will maintain a slightly higher standby current than standard
SPI operation. The Release from Power-down (ABh) can be
used to return to standard SPI standby current (ICC1). In
addition, Write Enable instruction (06h) and Power Down
instruction (B9h) will also release the device from HPM mode
back to standard SPI standby state.
Figure 27. High Performance Mode Instruction Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
tRES2
Instruction (A3)
3 Dummy Bytes
DI
23
21
2
1
22
3
0
MSB
High Performance
Current
DO
(April, 2016, Version 1.0)
37
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
