10.0 SCHEMATIC DIAGRAM
Two reference schematic diagrams are attached. Only one schematic, CKT 1, Sensor Board
Schematic, is required to represent both the sensor board 1 and 2 because the circuits are
identical. The second one is for the amplifier board it contains all eight of the amplifiers on one
schematic. The circuit description of its structure and operation has been briefly discussed in
section 1, DISCRIPTION, page 2. Its operation follows from the discussion of the simplified block
diagram. There are only two input control clocks for the circuits, the clock, CP, and the start
pulse, SP. SP starts the shift register scanning while CP clocks the register and produces the
video pixels at its same rate. The clocks are entered through the I/O connectors on both sensor
boards. They are both externally buffered with the 74HC00 hexes and applied to inputs of the
image sensors. On each of the two-image array sensor boards there are four sequential video
sections. Each video section contains a row of 5 sequential image array sensors, PI3039. These
are all clock in parallel with CP. The four sections on both boards are clocked with SP in parallel
to initiate all eight video sections and simultaneously begin the eight sequential readouts. All
eight lines, four in each sensor board, have reset switches, BU4S66, that parallel resets the
video pixel charges after they are readout. These pixels, readout in parallel, are applied to their
respective output amplifiers on the amplifier board.
The second schematic, CKT 2, Amplifier Board Schematic, is the amplifier board. There are eight
amplifiers for processing the output videos from both sensor boards. The amplifier board
receives the inputs from sensor board output connector, J1, through two harnesses. They are
connected into the input I/O connectors, J1 and J2, of the amplifier board. Since there are two
sensor boards using the same schematic representation, the connector on sensor board 1, J1,
becomes J2 for the second board. They are physically differentiated and marked as J1 and J2
on the Stiffener Board. Since all eight sections process their video signals through identical
amplifiers, only one amplifier circuit is discussed. The AD8051 is an operational amplifier that is
configured into non-inverting buffer amplifier with again of ≅ 4.5. It is used to isolate the video line
from its external circuits. The isolated video line then serves as a storage capacitance for the
pixels outputs. The pixel charges are read out onto the video line capacitance and integrated.
This integrated pixel charges, converted to a voltage pulse, is amplified and produced at the
output I/O. The reset switch on the video line, which is located on the sensor board schematic,
resets the pixel signal charge prior to the readout of following pixel.
11.0 DRAWING ON MECHANICAL STRUCTURE
Attached are 6 mechanical drawings. The first one, Top Assemble Outline, sheet 1of 1,
shows an outline drawing of the complete CIS system, consisting of the Stiffener Plate, the
interconnecting harness and the Amplifier Board. There are two connector Pin
Configuration Tables, one for the two sensor boards and the input for the amplifier board.
The other is for the two output connectors on the amplifier boards. These two tables show
the pin numbering and names for the 6 connectors that are seen in the drawing. For detail
descriptions of the interconnection and their functions, see section 9.0 CONNECTORS PIN
CONFIGURATION, page 9.
The second one, Stiffener Plate, is the view of the stiffener board. Stiffener board is ¼”
aluminum backing plate on which the two image sensor boards are mounted. It provides
the dimensions of the plate, its access holes for the two-sensor board’s connectors, along
with all of the required dimensions.
The third one, Two Sensor Board on the Stiffener, is a view of the two sensor boards
mounted on the stiffener board. It shows the direction of the scan, its first pixel location and
PAGE 11 OF 22 - PI616MC-AS, 12/20/02
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