FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
S
DEVICE ADDRESS
W A
REGISTER ADDRESS
A
DATA
A P
7-bit Receive
Device Address
START
Command
Register Address
Acknowledge
WRITE Command
From bus host
to device
Data
Acknowledge
STOP Condition
Acknowledge
From device
to bus host
Figure 5: Random Register Write Procedure
S
DEVICE ADDRESS
W A
REGISTER ADDRESS
A S
DEVICE ADDRESS
R A
DATA
A P
7-bit Receive
Device Address
START
Command
Register Address
Acknowledge
WRITE Command
From bus host
to device
7-bit Receive
Device Address
Repeat START
Acknowledge
From device
to bus host
Data
Acknowledge
READ Command
STOP Condition
NO Acknowledge
Figure 6: Random Register Read Procedure
S
DEVICE ADDRESS
W A
REGISTER ADDRESS
A
DATA
A
DATA
A
DATA
A P
7-bit Receive
Device Address
START
Command
Register Address
Acknowledge
WRITE Command
From bus host
to device
Data
Acknowledge
Data
Acknowledge
Acknowledge
Data
Acknowledge
STOP Command
From device
to bus host
Figure 7: Sequential Register Write Procedure
S
DEVICE ADDRESS
W A
REGISTER ADDRESS
A S
DEVICE ADDRESS
R A
DATA
A
DATA
A P
7-bit Receive
Device Address
START
Command
Register Address
Acknowledge
WRITE Command
From bus host
to device
7-bit Receive
Device Address
Repeat START
Acknowledge
From device
to bus host
Data
Acknowledge
READ Command
Acknowledge
Data
NO Acknowledge
STOP Command
Figure 8: Sequential Register Read Procedure
AMI Semiconductor
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