Data Sheet
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 4. Power-Down Bits
Table 5. Divider Control Bits
Name
Description
Name
Description
Power-Down PLL A
Bit = 0
REFDIV_A[7:0]
(Bits 7-0)
R
Reference Divider A (N )
Power on
Power off
PDPLL_A
(Bit 21)
Bit = 1
REFDIV_B[7:0]
(Bits 31-24)
R
Reference Divider B (N )
Power-Down PLL B
Bit = 0
Power on
Power off
PDPLL_B
(Bit 45)
R
Reference Divider C1 (N )
selected when the SEL-CD pin = 0
REFDIV_C1[7:0]
(Bits 55-48)
Bit = 1
Power-Down PLL C
Bit = 0
R
Reference Divider C2 (N )
REFDIV_C2[7:0]
(Bits 79-72)
Power on
Power off
PDPLL_C
(Bit 69)
selected when the SEL-CD pin = 1
Bit = 1
F
Feedback Divider A (N )
Reserved (0)
(Bit 69)
Set these reserved bits to zero (0)
FBKDIV_A[2:0]
FBKDIV_A[10:3]
A-Counter value
FBKDIV_A[10:0]
(Bits 18-8)
Power-Down POST divider A
M-Counter value
Bit = 0
Bit = 1
Power on
Power off
PDPOSTA
(Bit 120)
F
Feedback Divider B (N )
Power-Down POST divider B
FBKDIV_B[2:0]
FBKDIV_B[10:3]
A-Counter value
FBKDIV_B[10:0]
(Bits 42-32)
Bit = 0
Bit = 1
Power on
Power off
PDPOSTB
(Bit 121)
M-Counter value
F
Feedback Divider C1 (N )
selected when the SEL-CD pin = 0
Power-Down POST divider C
Bit = 0
Bit = 1
Power on
Power off
PDPOSTC
(Bit 122)
FBKDIV_C1[2:0]
FBKDIV_C1[10:3]
A-Counter value
FBKDIV_C1[10:0]
(Bits 66-56)
M-Counter value
Power-Down POST divider D
Bit = 0
Bit = 1
Power on
Power off
F
Feedback DividerC2 (N )
PDPOSTD
(Bit 123)
selected when the SEL-CD pin = 1
FBKDIV_C2[2:0]
FBKDIV_C2[10:3]
A-Counter value
M-Counter value
FBKDIV_C2[10:0]
(Bits 90-80)
Table 6. Divider Control Bits
Table 7. Post Divider Modulus
Name
Description
BIT [3]
BIT [2]
BIT [1]
BIT [0]
DIVIDE BY
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
POST_A[3:0]
(Bits 99-96)
POST divider A (see Table 7)
POST divider B (see Table 7)
POST_B[3:0]
(Bits 103-100)
3
4
POST_C1[3:0] POST divider C1 (see Table 7)
(Bits 107-104) selected when the SEL_CD pin = 0
5
6
POST_C2[3:0] POST divider C2 (see Table 7)
(Bits 115-112) selected when the SEL_CD pin = 1
8
9
POST_D1[3:0] POST divider D1 (see Table 7)
(Bits 111-108) selected when the SEL_CD pin = 0
10
12
15
16
18
20
25
50
POST_D2[3:0] POST divider D2 (see Table 7)
(Bits 119-116)
selected when the SEL_CD pin = 1
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