FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 1. Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
DI
u
O
DI
P
AI
AO
DI
u
P
DI
P
DO
DO
P
DO
DI
u
u
u
Data Sheet
Name
SDA
SEL_CD
PD
VSS
XIN
XOUT
OE
VDD
ADDR
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
SCL
Description
Serial interface data input/output
Selects one of two PLL C, mux D/C and post divider C/D combinations
Power-down input
Ground
Crystal oscillator input
Crystal oscillator output
Output enable input
Power supply (5V to 3.3V)
Address select
D clock output
Ground
C clock output
B clock output
Power supply (5V to 3.3V)
A clock output
Serial interface clock input
U
DI
u
DO
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input With Internal Pull-Up; DI
D
= Input With Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
3.0 Functional Block Description
3.1 Phase Locked Loops
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired
frequency by a ratio of integers. This frequency
multiplication is exact.
As shown in Figure 3, each PLL consists of a reference
divider, a phase-frequency detector (PFD), a charge
pump, an internal loop filter, a voltage-controlled oscillator
(VCO), and a feedback divider.
During operation, the reference frequency (f
REF
), generated
by the on-board crystal oscillator, is first reduced by the
reference divider. The divider value is called the
"modulus," and is denoted as N
R
for the reference divider.
The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (f
VCO
) through
the charge pump and loop filter. The VCO provides a high-
speed, low noise, continuously variable frequency clock
source for the PLL. The output of the VCO is fed back to
the PFD through the feedback divider (the modulus is
denoted by N
F
) to close the loop.
REFDIV[7:0]
CP
LFTC
Loop
Filter
f
REF
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
f
PD
UP
Charge
Pump
DOWN
FBKDIV[10:0]
Voltage
Controlled
Oscillator
f
VCO
Feedback
Divider
(N
F
)
Figure 3: PLL Diagram
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frquency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference
frequency and the VCO frequency is:
f
VCO
=
f
REF
( )
N
F
N
R
.
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