AMIS-720341-A: Contact Image Sensor
Data Sheet
12.0 Switching Characteristics at 25°C
The timing relationships of the video output voltage and its two input clocks, the SP and the shift register clock (CP), along with the shift
register (EOS) output clock are shown in Figure 11. The switch timing specification for the symbols on the timing diagram is given in
Table 9. The digital clocks' levels are +5V CMOS compatible. The video, IOUT, is defined in Figure 4.
Figure 11: Timing Diagram of the AMIS-720341-A Sensor
Table 9: Timing Symbol's Definition
Item
Symbol
Min.
200
50
25
20
Mean
Max.
10000
Units
ns
ns
%
ns
ns
ns
ns
ns
Clock cycle time
Clock pulse width(1)
Clock duty cycle
Data setup time
Data hold time
Prohibit crossing time(2)
EOS rise delay
EOS fall delay
Signal delay time(3)
Signal settling time(3)
Notes:
to
tw
50
75
tds
tdh
tprh
terdl
tefdl
tdl
20
20
60
70
20
120
ns
ns
ts/h
(1) The clock pulse width, tw, varies with frequency, as well as the duty cycle.
(2) Prohibit crossing time is to insure that no two SPs are locked into the shift register for any single scan time. Since the SP is entered into the shift register during
its active high level when the CP clock edges falls, the active high of the SP is permitted only during one falling, CP, clock edges for any given scan. Otherwise,
multiple SPs will load into the shift register.
(3) Pixel delay times and settling times depend on the employment of the output amplifier. These values, tdl and ts/h, are measured with the amplifier (see Figure
12) using the AMIS-720341-A sensors. Note that the impulse signal current out of the device has a pulse width ~ 30ns. Hence, the faster the amplifier with a
faster settling time will yield a signal video pulse with faster rise and settle times.
AMI Semiconductor – May 06, M-20570-001
13
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