FS6132
AMERICAN MICROSYSTEMS, INC.
VCXO Clock Generator IC
Preliminary
January 2000
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 5V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
Overall
Supply Current, Dynamic, with Loaded
Outputs
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF
20
mA
Voltage Controlled Crystal Oscillator - VDD=5.0V
Crystal Loading Capacitance
Crystal Resonator Motional Capacitance
VCXO Tuning Range
VCXO Tuning Characteristic
Crystal Drive Level
Clock Outputs (CLKA, CLKB) - VDDO=3.3V
High-Level Output Source Current *
Low-Level Output Sink Current *
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
I
OH
I
OL
z
OH
z
OL
I
OSH
I
OSL
V
O
= 2.0V
V
O
= 0.4V
output driving high
output driving low
V
O
= 0V; shorted for 30s, max.
V
O
= 5V; shorted for 30s, max.
C
L(xtal)
C
1(xtal)
As seen by a crystal connected to XIN and
XOUT (@ V
XTUNE
= 1.65V)
AT cut
f
XTAL
= 13.5MHz; C
L(xtal)
= 14pF; C
1(xtal)
= 25fF
Note: positive
∆F
for positive
∆V
R
XTAL
=20Ω; C
L(xtal)
= 14pF
14
25
300
100
200
-35
+20
30
25
-60mA
+60mA
pF
fF
ppm
ppm/V
uW
mA
mA
Ω
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 5V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3σ from typical.
PARAMETER
Overall
VCXO Stabilization Time *
PLL Stabilization Time *
Output Frequency Synthesis Error
Clock Outputs (CLKx)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Period (peak-peak) *
Jitter, Long Term (σ
y
(τ)) *
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
t
VCXOSTB
t
PLLSTB
From power valid
From VCXO stable
(unless otherwise noted in Frequency Table)
10
50
0
ms
us
ppm
Ratio of high pulse width (as measured from rising edge
to next falling edge at V
DD
/2) to one clock period
ALL
54MHz
27MHz
ALL
54MHz
27MHz
45
200
200
150
55
%
ps
ps
ps
dbC/Hz
t
j(∆P)
t
j(∆P)
t
j(LT)
From rising edge to next rising edge at V
DD
/2, C
L
= 10pF
From rising edge to next rising edge at V
DD
/2, C
L
= 10pF
RMS deviation compared to ideal clock source
@ 10KHz offset
Phase Noise *
Θ
N
@ 100KHz offset
@ 10KHz offset
@ 100KHz offset
dbC/Hz
Rise Time *
Fall Time *
t
r
t
f
V
DDO
= 3.3V; V
O
= 0.4V to 2.4V; C
L
= 10pF
V
DDO
= 3.3V; V
O
= 2.4V to 0.4V; C
L
= 10pF
1.0
1.0
ns
ns
5
ISO9001
1.24.00
AMI [ AMI SEMICONDUCTOR ]
