AMIS-42770 Dual High-Speed CAN Transceiver
For Long Networks
Data Sheet
Table 3: Function of the Logic Unit; bold letters describe input signals
EN1B
EN2B
TX0
TEXT
Bus 1 State
0
0
0
0
dominant
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Note:
(1)
Dominant detected by the corresponding receiver.
Bus 2 State
dominant
RX0
0
RINT
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
dominant
dominant
recessive
dominant
(1)
dominant
dominant
recessive
dominant
dominant
(1)
0
0
1
0
0
0
0
0
1
0
(1)
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
dominant
dominant
dominant
dominant
recessive
dominant
(1)
recessive
recessive
recessive
recessive
recessive
dominant
recessive
recessive
recessive
recessive
recessive
dominant
(1)
1
0
0
0
1
1
dominant
dominant
dominant
recessive
recessive
dominant
(1)
recessive
recessive
recessive
recessive
recessive
dominant
(1)
0
0
0
0
1
1
recessive
recessive
recessive
recessive
recessive
dominant
(1)
recessive
1
7.4 Receivers
Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and
accurate comparator. The aim of the input filter is to improve the immunity against high-frequency disturbances and also to
convert the voltage at the bus lines CANHx and CANLx, which can vary from –12V to +12V, to voltages in the range 0 to 5V, which
can be applied to the comparators.
The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high), the output signal of the
comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. In the enabled state the
receiver signal sent to the logic unit is identical to the comparator output signal.
7.5 Time-out Counter
To avoid that the transceiver drives a permanent dominant state on either of the bus lines (blocking all communication), time-out
function is implemented. Signals on pins Tx0 and Text as well as both bus receivers are connected to the logic unit through
independent timers. If the input of the timer stays dominant for longer than 25ms (see parameter t
dom
), it is replaced by a recessive
signal on the timer output.
7.6 Feedback Suppression
The logic unit described in Table 3 constantly ensures that dominant symbols on one bus line are transmitted to the other bus line
without imposing any priority on either of the lines. This feature would lead to an “interlock” state with permanent dominant signal
transmitted to both bus lines, if no extra measure is taken.
Therefore a feedback suppression is included inside the logic unit of the transceiver. This block masks-out reception on that bus
line, on which a dominant is actively transmitted. The reception becomes active again only with certain delay after the dominant
transmission on this line is finished.
AMI Semiconductor
– October 2007, Rev. 1.0
www.amis.com
Specifications subject to change without notice
7
AMI [ AMI SEMICONDUCTOR ]
