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ELANSC400-66AC 参数 Datasheet PDF下载

ELANSC400-66AC图片预览
型号: ELANSC400-66AC
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片,低功耗, PC / AT兼容的微控制器 [Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers]
分类和应用: 微控制器PC
文件页数/大小: 132 页 / 2249 K
品牌: AMD [ AMD ]
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Fast page and Extended Data Out (EDO) DRAMs  
ROM/Flash Memory Interface  
Two-way interleaved operation among identically  
The integrated ROM/Flash memory interface supports  
the following features:  
populated banks using fast-page mode devices  
Mixed depth and width of DRAM banks in non-inter-  
8-, 16-, and 32-bit ROM/Flash memory interfaces  
Three ROM/Flash memory chip selects  
Burst-mode ROMs  
leaved mode  
Symmetrical and asymmetrical DRAM support  
Integrated Standard PC/AT Peripherals  
ROM accesses at both ISA and CPU speeds  
(normal and fast-speed modes)  
The ÉlanSC400 and ÉlanSC410 microcontrollers in-  
clude all the standard peripheral controllers that make  
up a PC/AT system.  
Dedicated ROM Read and ROM Write signals for  
better performance  
Dual DMA Controllers  
Each ROM space can accommodate up to 64 Mbyte of  
ROM. The three ROM spaces can be individually write-  
protected. This is useful for protecting code residing in  
Flash memory devices.  
Dual, cascaded, 8237A-compatible DMA controllers  
provide seven user-definable DMA channels. Of the  
seven internal channels, four are 8-bit channels and  
three are 16-bit channels. Channel 4 is used for the cas-  
cade function.  
Two of the three ROM/Flash memory chip selects can  
be remapped to a PC Card socket via pinstrap or soft-  
ware control. This feature supports reprogramming of  
soldered-down Flash memory boot devices and also  
simplifies testing of BIOS/XIP OS code.  
Any two of the seven channels can be mapped simul-  
taneously to external DMA request/acknowledge lines.  
The DMA controller on the ÉlanSC400 and ÉlanSC410  
microcontrollers is software compatible with the PC/AT  
cascaded 8237 controller pair. Its features include:  
Three ROM access modes are supported: Normal  
mode, Fast mode, and Burst mode. A different set of  
timings is used in each mode. In Normal ROM access  
mode, the bus cycles follow ISA-like timings. In Fast  
ROM access mode, the bus cycle timing occurs at the  
CPU clock rate with controls for wait-state insertion.  
Burst ROM access timing is used when the ROM/Flash  
memory interface is fulfilling an internal CPU burst re-  
quest to support a cache line refill.  
Single, block, and demand transfer modes  
Enable/disable channel controller  
Address increment or decrement  
Software priority  
64-Mbyte system address space for increased  
performance  
Wait states are supported for all ROM and Flash mem-  
ory accesses, including Burst mode. Burst-mode  
(page-mode) ROM reads are supported for either a  
16- or 32-bit ROM interface running in Fast mode.  
Dynamic clock-enable design for reducing clocked  
elements during DMA inactivity  
Programmable clock frequency for performance  
Dual Interrupt Controllers  
DRAM Controller  
Dual, cascaded, 8259-compatible programmable  
interrupt controllers support 15 user-definable interrupt  
levels. Eight external interrupt requests can be mapped  
to any of the 15 internal IRQ inputs.  
The integrated DRAM controller provides the signals and  
associated timing necessary to support an external  
DRAM array with minimal software programming and  
overhead. Internal programmable registers are provided  
to select the DRAM type and operating mode, as well as  
refresh options. A wide variety of commodity DRAMs are  
supported, and substantial flexibility is built into the DRAM  
controller to optimize performance of the CPU and (on the  
ÉlanSC400 microcontroller) the internal graphics control-  
ler, which uses system DRAM for its buffers.  
The interrupt controller block includes these features:  
Software-compatibility with PC/AT interrupt controllers  
15-level priority controller  
Programmable interrupt modes  
Individual interrupt request mask capability  
Accepts requests from peripherals  
The DRAM controller supports the following features:  
3.3-V, 70-ns DRAMs  
Up to four banks  
Resolves priority on pending interrupts and  
interrupts in service  
16-bit or 32-bit banks  
Up to 64 Mbyte of total memory  
Self-refresh DRAMs  
Issues interrupt request to processor  
Provides interrupt vectors for interrupt service routines  
Tied into the PMU for power management  
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet  
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