Figure 35. DRAM Page Hit Read, Non-Interleaved .............................................................. 100
Figure 36. DRAM Page Hit Write, Non-Interleaved .............................................................. 101
Figure 37. DRAM Page Miss Read, Non-Interleaved ........................................................... 101
Figure 38. EDO DRAM Page Hit Read, Non-Interleaved ..................................................... 102
Figure 39. EDO DRAM Page Miss Read, Non-Interleaved .................................................. 102
Figure 40. DRAM CAS-Before-RAS Refresh ........................................................................ 103
Figure 41. DRAM Self-Refresh ............................................................................................. 103
Figure 42. DRAM Slow Refresh ............................................................................................ 104
Figure 43. 8-Bit ISA Bus Cycles ............................................................................................ 107
Figure 44. 16-Bit ISA Bus Cycles .......................................................................................... 108
Figure 45. ISA DMA Read Cycle .......................................................................................... 109
Figure 46. ISA DMA Write Cycle ........................................................................................... 110
Figure 47. VESA Local Bus Cycles ....................................................................................... 112
Figure 48. EPP Parallel Port Write Cycle .............................................................................. 114
Figure 49. EPP Parallel Port Read Cycle ............................................................................. 115
Figure 50. I/O Decode (R/W), Address Decode Only ........................................................... 116
Figure 51. I/O Decode (R/W), Command Qualified .............................................................. 116
Figure 52. I/O Decode (R/W), GPIO_CSx as 8042CS Timing .............................................. 117
Figure 53. Memory CS Decode (R/W), Address Decode Only ............................................. 117
Figure 54. Memory CS Decode (R/W), Command Qualified ................................................ 118
Figure 55. PC Card Attribute Memory Read Cycle (ÉlanSC400 Microcontroller Only) ........ 120
Figure 56. PC Card Attribute Memory Write Cycle (ÉlanSC400 Microcontroller Only) ......... 121
Figure 57. PC Card Common Memory Read Cycle (ÉlanSC400 Microcontroller Only) ....... 122
Figure 58. PC Card Common Memory Write Cycle (ÉlanSC400 Microcontroller Only) ....... 123
Figure 59. PC Card I/O Read Cycle ...................................................................................... 124
Figure 60. PC Card I/O Write Cycle ...................................................................................... 125
Figure 61. PC Card DMA Read Cycle (Memory Read to I/O Write) ..................................... 126
Figure 62. PC Card DMA Write Cycle (I/O Read to Memory Write) ..................................... 127
Figure 63. Graphics Panel Interface Timing (ÉlanSC400 Microcontroller Only) ................... 128
Figure 64. Graphics Panel Power Sequencing (ÉlanSC400 Microcontroller Only) .............. 129
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Product Comparison—ÉlanSC400 and ÉlanSC410 Microcontrollers ...................... 3
Drive Output Description ........................................................................................ 40
Pin Type Abbreviations .......................................................................................... 40
Power Pin Type Abbreviations ............................................................................... 41
Power-Down Groups ............................................................................................. 41
Pin State Table—System Interface ........................................................................ 42
Pin State Table—Memory Interface ....................................................................... 44
Pin State Table—GPIOs/Parallel Port/PC Card Socket B ..................................... 47
Pin State Table—GPIOs/ISA Bus .......................................................................... 49
Table 10. Pin State Table—GPIOs/System Data (SD) Buffer Control ................................... 51
Table 11. Pin State Table—GPIOs ........................................................................................ 52
Table 12. Pin State Table—Serial Port .................................................................................. 52
Table 13. Pin State Table—Infrared Interface ....................................................................... 52
Table 14. Pin State Table—Keyboard Interface .................................................................... 53
Table 15. Pin State Table—PC Card Socket A ..................................................................... 55
Table 16. Pin State Table—Graphics Controller/VESA Local Bus Control ............................ 56
Table 17. Pin State Table—Miscellaneous ............................................................................ 58
Table 18. Pin State Table—Power and Ground .................................................................... 59
Table 19. Signal Description Table ........................................................................................ 62
Table 20. Multiplexed Pin Configuration Options ................................................................... 70
Table 21. Pinstrap Bus Buffer Options .................................................................................. 74
10
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
