TBR17: 10BASE-T PHY Control/Status Register
(Register 17)
This register is used to control the configuration of the
10 Mbps PHY unit of the Am79C978 home networking
device. See Table 75.
Table 75. TBR17: 10BASE-T PHY Control/Status Register (Register 17)
H/W
Bits
Name
Description
Read/Write
Reset
Soft Reset
Retains
Previous
Value
15
Reserved
R/W
0
Retains
Previous
Value
14
Reserved
R/W
0
1 = link status forced to link up state
Force Link Good
Enable
13
12
R/W
R/W
0
0
0
0
0 = link status is determined by the device
1 = Link pulses sent from the
Disable Link Pulse
10BASE-T transmitter are suppressed
1 = Disables the SQE heartbeat which occurs
after each 10BASE-T transmission
11
SQE_TEST Disable
R/W
0
0
0 = The heart beat assertion occurs on the
COL pin approximately 1 µs after transmission
and for a duration of 1 µs.
10
9
Reserved
Jabber Detect Disable
Reserved
R/W
R/W
R/W
0
0
0
0
1 = disable jabber detect
0 = enable jabber detect
8:7
00
00
1 = Receive polarity of the 10BASE-T receiver
is reversed
Receive Polarity
Reversed
6
5
RO
0
0
0
0
0 = Receive polarity is correct
1 = polarity correction circuit is disabled for
10BASE-T
Auto Receive Polarity
Correction Disable
R/W
0 = Self correcting polarity circuit is enabled
1 = 10BASE-T receive squelch thresholds are
reduced to allow reception of frames which are
greater than 100 meters
Extended Distance
Enable
4
R/W
0
0
0 = Squelch thresholds are set for standard
distance of 100 meters
1 = TX± outputs not active for 10BASE-T. TX±
outputs to logical “0” for PECL.
TX_DISABLE
TX_CRS_EN
3
2
R/W
RO
0
0
0
0
0 = Transmit valid data
1 = CRS is asserted when transmit or receive
medium is active
0 = CRS is asserted when receive medium is
active
1
0
Reserved
RO
RO
0
0
1 = Internal PHY is isolated
0 = Internal PHY is enabled
PHY Isolated
0/1
0/1
Note:
1. For these loopback paths, the data is also transmitted out of the MDI pins (TX±).
196
Am79C978
AMD [ AMD ]
