P R E L I M I N A R Y
Te st Cond iti on s
Table 7. Test Specifications
-90,
3.3
Test Condition
-70
-120
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance,
C
30
100
pF
L
C
6.2 kΩ
L
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–3.0
Input timing
measurement reference
levels
Note: Diodes are IN3064 or
1.5
V
V
Figure 1. Test Setup
Output timing
measurement reference
levels
1.5
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 1. Input Waveforms and
Measurement Levels
30
Am29LV800D
Am29LV800D_00_A4_E January 21, 2005
AMD [ AMD ]
