D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
100, 110,
120,
90R 100R 110R 120R Unit
JEDEC
tAVAV
Std.
tWC
tAS
Description
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
100
110
120
ns
ns
ns
ns
ns
tAVWL
tELAX
tDVEH
tEHDX
0
45
45
0
tAH
tDS
tDH
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
0
0
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
sec
ns
WE# Hold Time
CE# Pulse Width
45
30
240
7.5
15
tCPH
CE# Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Per Byte
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Per Byte
Per Word
Byte
6.25
12.5
60
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
Single Word/Byte Program Operation
(Note 2, 5)
Typ
Typ
Word
60
Byte
54
Accelerated Single Word/Byte
Programming Operation (Note 2, 5)
Word
54
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
tRH RESET# High Time Before Write (Note 1)
Typ
Min
0.5
50
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words (or 1–32 bytes in byte mode) programmed.
4. Effective write buffer specification is based upon a 16-word (or 32-byte) write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
May 16, 2003
Am29LV320MT/B
51
AMD [ AMD ]
