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AM29F016-120EC 参数 Datasheet PDF下载

AM29F016-120EC图片预览
型号: AM29F016-120EC
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2,097,152 ×8位) CMOS 5.0伏只,扇区擦除闪存 [16-Megabit (2,097,152 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 36 页 / 220 K
品牌: AMD [ AMD ]
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Table 1. Am29F016 User Bus Operations  
Operation  
Autoselect, AMD Manuf. Code (1)  
Autoselect Device Code (1)  
Read  
CE  
L
OE  
L
WE  
H
H
X
A0  
L
A1  
L
A6  
L
A9  
VID  
VID  
A9  
X
DQ0DQ7  
Code  
Code  
DOUT  
HIGH Z  
HIGH Z  
DIN  
RESET  
H
H
L
L
H
L
L
L
L
A0  
X
A1  
X
A6  
X
H
Standby  
H
L
X
X
H
Output Disable  
H
H
VID  
L
H
L
X
X
X
X
H
Write  
L
A0  
X
A1  
X
A6  
X
A9  
VID  
VID  
X
H
Enable Sector Group Protect (2)  
Verify Sector Group Protect (2)  
Temporary Sector Group Unprotect  
Hardware Reset/Standby  
Legend:  
L
L
X
H
L
H
X
L
H
L
Code  
X
H
X
X
X
X
X
X
VID  
L
X
X
X
X
X
X
HIGH Z  
L = logic 0, H = logic 1, X = Don’t Care. See DC Characteristics for voltage levels.  
Notes:  
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.  
2. Refer to the section on Sector Group Protection.  
Read Mode  
The Am29F016 has two control functions which must  
be satisfied in order to obtain data at the outputs. CE is  
the power control and should be used for device selec-  
tion. OE is the output control and should be used to  
gate data to the output pins if the device is selected.  
reduced to less than 1 µA. A TTL standby mode is  
achieved with CE and RESET pins held at VIH. Under  
this condition the current is typically reduced to 200 µA.  
The device can be read with standard access time (tCE  
)
from either of these standby modes.  
Address access time (tACC) is equal to the delay from  
stable addresses to valid output data. The chip  
enable access time (tCE) is the delay from stable  
addresses and stable CE to valid data at the output  
pins. The output enable access time is the delay from  
the falling edge of OE to valid data at the output pins  
(assuming the addresses have been stable for at  
least tACC–tOE time).  
When using the RESET pin only, a CMOS standby  
mode is achieved with RESET input held at VSS ± 0.3 V  
(CE = don’t care). Under this condition the current is typ-  
ically reduced to less than 1 µA. A TTL standby mode is  
achieved with RESET pin held at VIL (CE = don’t care).  
Under this condition the current is typically reduced to  
less than 200 µA. Once the RESET pin is taken high,  
the device requires 50 ns of wake up time before out-  
puts are valid for read access.  
Standby Mode  
In the standby mode the outputs are in the high imped-  
ance state, independent of the OE input.  
There are two ways to implement the standby mode on  
the Am29F016 device, one using both the CE and  
RESET pins; the other via the RESET pin only.  
Output Disable  
When using both pins, a CMOS standby mode is  
achieved with CE and RESET inputs both held at VCC  
± 0.3 V. Under this condition the current is typically  
With the OE input at a logic high level (VIH), output from  
the device is disabled. This will cause the output pins to  
be in a high impedance state.  
8
Am29F016