D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
tREADY
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
500
50
ns
ns
RESET# High Time Before Read (See Note)
Note: Not 100% tested. RESET# is not available on Am29F002NB.
CE#, OE#
tRH
RESET#
n/a Am29F002NB
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002NB
tRP
Figure 10. RESET# Timings
26
Am29F002B/Am29F002NB
21527D5 November 1, 2006
AMD [ AMD ]
