D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-55
-70
-90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
55
70
90
90
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
70
ns
tELQV
tGLQV
tEHQZ
tCE
tOE
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
55
30
15
70
30
20
90
35
20
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z
(Note 1)
tGHQZ
tDF
tOEH
tOH
Max
Min
Min
15
20
0
20
ns
ns
ns
Read
Output Enable
Hold Time
(Note 1)
Toggle and
Data# Polling
10
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
Min
0
ns
Notes:
1. Not 100% tested.
2. See Table 7 and Figure 8 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
n/a Am29F002NB
Figure 9. Read Operations Timings
November 1, 2006 21527D5
Am29F002B/Am29F002NB
25
AMD [ AMD ]
