P R E L I M I N A R Y
CHIP-SELECT UNIT
The Am186ES and Am188ES microcontrollers contain
logic that provides programmable chip-select genera-
tion for both memories and peripherals. The logic can
be programmed to provide ready and wait-state gener-
ation and latched address bits A1 and A2. The chip-se-
lect lines are active for all memory and I/O cycles in
their programmed areas, whether they are generated
by the CPU or by the integrated DMA unit.
The ARDY signal on the Am186ES and Am188ES mi-
crocontrollers is a true asynchronous ready signal. The
ARDY pin accepts a rising edge that is asynchronous
to CLKOUTA and is active High. If the falling edge of
ARDY is not synchronized to CLKOUTA as specified,
an additional clock period may be added.
Chip-Select Overlap
Although programming the various chip selects on the
Am186ES microcontroller so that multiple chip select
signals are asserted for the same physical address is
not recommended, it may be unavoidable in some sys-
tems. In such systems, the chip selects whose asser-
tions overlap must have the same configuration for
ready (external ready required or not required) and the
number of wait states to be inserted into the cycle by
the processor.
The Am186ES and Am188ES microcontrollers provide
six chip-select outputs for use with memory devices
and six more for use with peripherals in either memory
space or I/O space. The six memory chip selects can
be used to address three memory ranges. Each periph-
eral chip select addresses a 256-byte block that is off-
set from a programmable base address. A write to a
chip select register will enable the corresponding chip
select logic even if the actual pin has another function
(e.g., PIO).
The peripheral control block (PCB) is accessed using
internal signals. These internal signals function as chip
selects configured with zero wait states and no external
ready. Therefore, the PCB can be programmed to ad-
dresses that overlap external chip-select signals only if
those external chip selects are programmed to zero
wait states with no external ready required.
Chip-Select Timing
The timing for the UCS and LCS outputs is modified
from the original 80C186 microcontroller. These out-
puts now assert in conjunction with the nonmultiplexed
address bus for normal memory timing. To allow these
outputs to be available earlier in the bus cycle, the num-
ber of programmable memory size selections has been
reduced.
When overlapping an additional chip select with either
the LCS or UCS chip selects, it must be noted that set-
ting the Disable Address (DA) bit in the LMCS or UMCS
register disables the address from being driven on the
AD bus for all accesses for which the associated chip
select is asserted, including any accesses for which
multiple chip selects assert.
Ready and Wait-State Programming
The Am186ES and Am188ES microcontrollers can be
programmed to sense a ready signal for each of the
peripheral or memory chip-select lines. The ready sig-
nal can be either the ARDY or SRDY signal. Each chip-
select control register (UMCS, LMCS, MMCS, PACS,
and MPCS) contains a single-bit field that determines
whether the external ready signal is required or
ignored.
The MCS and PCS chip-select pins can be configured
as either chip selects (normal function) or as PIO inputs
or outputs. It should be noted; however, that the ready
and wait state generation logic for these chip selects is
in effect regardless of their configurations as chip se-
lects or PIOs. This means that if these chip selects are
enabled (by a write to the MMCS and MPCS for the
MCS chip selects, or by a write to the PACS and MPCS
registers for the PCS chip selects), the ready and wait
state programming for these signals must agree with
the programming for any other chip selects with which
their assertion would overlap if they were configured as
chip selects.
The number of wait states to be inserted for each ac-
cess to a peripheral or memory region is programma-
ble. The chip-select control registers for UCS, LCS,
MCS3–MCS0, PCS6, and PCS5 contain a two-bit field
that determines the number of wait states from zero to
three to be inserted. PCS3–PCS0 use three bits to pro-
vide additional values of 5, 7, 9, and 15 wait states.
When external ready is required, internally pro-
grammed wait states will always complete before exter-
nal ready can terminate or extend a bus cycle. For
example, if the internal wait states are set to insert two
wait states, the processor samples the external ready
pin during the first wait cycle. If external ready is as-
serted at that time, the access completes after six cy-
cles (four cycles plus two wait states). If external ready
is not asserted during the first wait cycle, the access is
extended until ready is asserted, and one more wait
state occurs followed by t4.
Although the PCS4 signal is not available on an exter-
nal pin, the ready and wait state logic for this signal still
exists internal to the part. For this reason, the PCS4 ad-
dress space must follow the rules for overlapping chip
selects. The ready and wait-state logic for PCS6–
PCS5 is disabled when these signals are configured as
address bits A2–A1.
Failure to configure overlapping chip selects with the
same ready and wait state requirements may cause
the processor to hang with the appearance of waiting
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Am186/188ES and Am186/188ESLV Microcontrollers
AMD [ AMD ]
