P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
PSRAM Write Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Responses
20 MHz
Min
25 MHz
Min
No. Symbol
Max
Max Unit
5
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
AD Address Valid Delay and BHE
Data Valid Delay
0
0
0
25
25
0
0
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Status Hold Time
9
ALE Active Delay
ALE Width
25
20
10
11
20
23
80
81
84
tCLCL–10=40
tCLCL–10=30
ALE Inactive Delay
25
25
20
20
tCVCTV Control Active Delay 1(b)
0
0
tLHAV ALE High to Address Valid
20
15
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
0
25
25
0
20
20
0
0
tLRLL
LCS Precharge Pulse Width
tCLCL + tCLCH –3
tCLCL + tCLCH –3
Write Cycle Timing Responses
30
31
32
33
34
65
tCLDOX Data Hold Time
tCVCTX Control Inactive Delay(b)
0
0
ns
ns
ns
ns
ns
ns
0
25
0
20
tWLWH WR Pulse Width
2tCLCL–10=90
tCLCH–2
tCLCL–10=40
2tCLCL–10=70
tCLCH–2
tCLCL–10=30
tWHLH
tWHDX Data Hold after WR(a)
WR Inactive to ALE High(a)
tAVWL
tCHAV
tAVBL
A Address Valid to WR Low
tCLCL+tCHCL
–3
t
CLCL+tCHCL
–3
68
87
CLKOUTA High to A
Address Valid
0
25
25
0
20
20
ns
ns
A Address Valid to WHB, WLB
Low
tCHCL–3
tCHCL–3
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, WR, WHB, and WLB signals.
Am186/188ES and Am186/188ESLV Microcontrollers
77
AMD [ AMD ]
