P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
PSRAM Read Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
General Timing Requirements
33 MHz
Min
40 MHz
Min
No. Symbol
Max
Max Unit
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold(b)
8
3
5
2
ns
ns
General Timing Responses
5
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tLHAV
AD Address Valid Delay and BHE
Data Valid Delay
0
0
0
15
15
0
0
0
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Status Hold Time
9
ALE Active Delay
15
12
10
11
23
80
81
84
ALE Width
tCLCL–10=20
tCLCL–5=20
ALE Inactive Delay
ALE High to Address Valid
15
12
10
7.5
0
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
0
15
15
12
12
0
0
tLRLL
LCS Precharge Pulse Width
tCLCL + tCLCH –3
tCLCL + tCLCH
1.25
–
Read Cycle Timing Responses
24
25
26
27
28
59
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHDX
AD Address Float to RD Active
RD Active Delay
0
0
0
ns
ns
ns
ns
ns
ns
0
15
15
10
12
RD Pulse Width
2tCLCL–15=45
2tCLCL–10=40
RD Inactive Delay
RD Inactive to ALE High(a)
0
tCLCH–3
0
0
tCLCH–1.25
0
RD High to Data Hold on AD
Bus(b)
66
68
tAVRL
tCHAV
A Address Valid to RD Low
tCLCL+ tCHCL–3
0
tCLCL+ tCHCL
–
ns
ns
1.25
CLKOUTA High to A Address
Valid
15
0
10
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC –0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186/188ES and Am186/188ESLV Microcontrollers
75
AMD [ AMD ]
