The third is an internal interrupt from the asynchronous
serial port.
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) automatically generates
refresh bus cycles. After a programmable period of time,
the RCU generates a memory read request to the bus in-
terface unit. If the address generated during a refresh bus
cycle is within the range of a properly programmed chip
select, that chip select (with the exception of UCS and
LCS) is activated when the bus interface unit executes the
refresh bus cycle. The ready logic and wait states pro-
grammed for the region are also in force. If no chip select
is activated, then external ready is required to terminate
the refresh bus cycle.
The five maskable interrupt request pins can be used
as direct interrupt requests. Plus, INT3–INT0 can be
cascaded with an 82C59A-compatible external inter-
rupt controller if more inputs are needed. An external
interrupt controller can be used as the system master
by programming the internal interrupt controller to op-
erate in slave mode. In all cases, nesting can be en-
abled so that service routines for lower priority
interrupts are interrupted by a higher priority interrupt.
Programming the Interrupt Control Unit
If the HLDA pin is active when a refresh request is gen-
erated (indicating a bus hold condition), then the
Am186ER and Am188ER microcontrollers deactivate
the HLDA pin in order to perform a refresh cycle. The
external bus master must remove the HOLD signal for
at least one clock in order to allow the refresh cycle to
execute. The sequence of HLDA going inactive while
HOLD is being held active can be used to signal a
pending refresh request.
The Am186ER and Am188ER microcontrollers provide
two methods for masking and unmasking the maskable
interrupt sources. Each interrupt source has an inter-
rupt control register (offsets 32h–44h) that contains a
mask bit specific to that interrupt. In addition, the Inter-
rupt Mask Register (offset 28h) is provided as a single
source to access all of the mask bits. While changing a
mask bit in either the mask register or the individual
register will change the corresponding mask bit in the
other register, there is a difference in exactly how the
mask is updated.
The Am186ER and Am188ER microcontrollers’ HOLD
latency time, the period between HOLD request and
HOLD acknowledge, is a function of the activity occur-
ring in the processor when the HOLD request is re-
ceived. A HOLD request is second only to DRAM
refresh requests in priority of activity requests received
by the processor. For example, in the case of a DMA
transfer, the HOLD latency can be as great as four bus
cycles. This occurs if a DMA word transfer operation is
taking place from an odd address to an odd address
(Am186ER microcontroller only). This is a total of 16 or
more clock cycles if wait states are required. In addition,
if locked transfers are performed, the HOLD latency
time is increased by the length of the locked transfer.
If the Interrupt Mask Register is written while interrupts
are enabled, it is possible that an interrupt could occur
while the register is in an undefined state. This can
cause interrupts to be accepted even though they were
masked both before and after the write to the Interrupt
Mask Register. Therefore, the Interrupt Mask Register
should only be written when interrupts are disabled.
Mask bits in the individual interrupt control registers
can be written while interrupts are enabled, and there
will be no erroneous interrupt operation.
TIMER CONTROL UNIT
There are three 16-bit programmable timers in the
Am186ER and Am188ER microcontrollers. Timer 0 and
timer 1 are connected to four external pins (each has an
input and an output). These two timers can be used to
count, time external events, or generate nonrepetitive or
variable-duty-cycle waveforms. In addition, timer 1 can
be configured as a watchdog timer interrupt.
INTERRUPT CONTROL UNIT
The Am186ER and Am188ER microcontrollers can re-
ceive interrupt requests from a variety of sources, both
internal and external. The internal interrupt controller
arranges these requests by priority and presents them
one at a time to the CPU.
There are six external interrupt sources on the
Am186ER/Am188ER microcontrollers—five maskable
interrupt pins and one nonmaskable interrupt pin. In ad-
dition, there are six total internal interrupt sources—
three timers, two DMA channels, and the asynchronous
serial port—that are not connected to external pins.
Note that a hardware watchdog timer (WDT) has been
added to the Am186ER and Am188ER microcontrollers.
Use of the WDT is recommended for applications requir-
ing this reset functionality. To maintain compatibility with
previous versions of the Am186ER and Am188ER mi-
crocontrollers, Timer 1 can be configured as a watchdog
timer and can generate a maskable watchdog timer in-
terrupt. The maskable watchdog timer interrupt provides
a mechanism for detecting software crashes or hangs.
The TMROUT1 output is internally connected to the
watchdog timer interrupt. The TIMER1 Count Register
must then be reloaded at intervals less than the TIMER1
max count to assure the watchdog interrupt is not taken.
The Am186ER and Am188ER microcontrollers provide
three interrupt sources not present on the Am186 and
Am188 microcontrollers. The first is an additional exter-
nal interrupt pin (INT4), which operates much like the
already existing interrupt pins (INT3–INT0). The sec-
ond is an internal maskable watchdog timer interrupt.
Am186TMER and Am188TMER Microcontrollers Data Sheet
53
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