ered overlapping of the chip selects. Overlapping chip
selects refers to configurations where more than one
chip select asserts for the same physical address.
Chip-Select Overlap
Although programming the various chip selects on the
Am186ER microcontroller so that multiple chip select
signals are asserted for the same physical address is
not recommended, it may be unavoidable in some sys-
tems. In such systems, the chip selects whose asser-
tions overlap must have the same configuration for
ready (external ready required or not required) and the
number of wait states to be inserted into the cycle by
the processor.
Upper Memory Chip Select
The Am186ER and Am188ER microcontrollers provide
a UCS chip select for the top of memory. On reset, the
Am186ER and Am188ER microcontrollers begin fetch-
ing and executing instructions starting at memory loca-
tion FFFF0h. Therefore, upper memory is usually used
as instruction memory. To facilitate this usage, UCS de-
faults to active on reset, with a default memory range of
64 Kbyte from F0000h to FFFFFh, with external ready
required and three wait states automatically inserted.
The UCS memory range always ends at FFFFFh. The
lower boundary is programmable. The Upper Memory
Chip Select is configured through the Upper Memory
Chip Select (UMCS) Register.
The peripheral control block (PCB) and the internal
memory are both accessed using internal signals.
These internal signals function as chip selects config-
ured with zero wait states and no external ready. There-
fore, the PCB and internal memory can be
programmed to addresses that overlap external chip
select signals if those external chip selects are pro-
grammed to zero wait states with no external ready re-
quired.
During the address phase of a bus cycle when UCS is
asserted, the DA bit in the UMCS Register enables or
disables the AD15–AD0 bus. If the DA bit is set to 1,
AD15–AD0 is not driven during the address phase of a
bus cycle when UCS is asserted. If DA is cleared to 0,
AD15–AD0 is driven during the address phase of a bus
cycle. Disabling AD15–AD0 reduces power consump-
tion and eliminates potential bus conflicts with memory
or peripherals at high clock rates. The DA bit in the
UMCS Register defaults to 0 at power-on reset.
When overlapping an additional chip select with either
the LCS or UCS chip selects, it must be noted that set-
ting the Disable Address (DA) bit in the LMCS or UMCS
register will disable the address from being driven on
the AD bus for all accesses for which the associated
chip select is asserted, including any accesses for
which multiple chip selects assert.
The MCS and PCS chip select pins can be configured
as either chip selects (normal function) or as PIO inputs
or outputs. It should be noted; however, that the ready
and wait state generation logic for these chip selects is
in effect regardless of their configurations as chip se-
lects or PIOs. This means that if these chip selects are
enabled (by a write to the MMCS and MPCS for the
MCS chip selects, or by a write to the PACS and MPCS
registers for the PCS chip selects), the ready and wait
state programming for these signals must agree with
the programming for any other chip selects with which
their assertion would overlap if they were configured as
chip selects.
Low Memory Chip Select
The Am186ER and Am188ER microcontrollers provide
an LCS chip select for the bottom of memory. Because
the interrupt vector table is located at the bottom of
memory starting at 00000h, the LCS pin has tradition-
ally been used to control data memory. The LCS pin is
not active on reset. The Am186ER and Am188ER mi-
crocontrollers also allow the IMCS Register and inter-
nal memory to be programmed to address 0. This
would allow the internal memory to be used for the in-
terrupt vector table and data memory.
Midrange Memory Chip Selects
Although the PCS4 signal is not available on an exter-
nal pin, the ready and wait state logic for this signal still
exists internal to the part. For this reason, the PCS4 ad-
dress space must follow the rules for overlapping chip
selects. The ready and wait-state logic for PCS6–PCS5
is disabled when these signals are configured as ad-
dress bits A2–A1.
The Am186ER and Am188ER microcontrollers provide
four chip selects, MCS3–MCS0, for use in a user-locat-
able memory block. The base address of the memory
block can be located anywhere within the 1-Mbyte
memory address space, exclusive of the areas associ-
ated with the UCS and LCS chip selects, as well as the
address range of the Peripheral Chip Selects, PCS6,
PCS5, and PCS3–PCS0, if they are mapped to mem-
ory. The MCS address range can overlap the PCS ad-
dress range if the PCS chip selects are mapped to I/O
space.
Failure to configure overlapping chip selects with the
same ready and wait state requirements may cause the
processor to hang with the appearance of waiting for a
ready signal. This behavior may occur even in a system
in which ready is always asserted (ARDY or SRDY tied
High).
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the multiplexed AD address bus.
Configuring PCS in I/O space with LCS or any other chip
select configured for memory address 0 is not consid-
Am186TMER and Am188TMER Microcontrollers Data Sheet
51
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